1. Technical Field
A method of forming a contact hole in a semiconductor device is disclosed, and more particularly, a method of manufacturing a capacitor in a semiconductor device is disclosed that prevents reduction of capacitance of the capacitor by improving the etching profile of the contact hole in which a charge storage electrode is formed.
2. Description of the Related Art
As the cell size of semiconductor devices is reduced, the height of the charge storage electrode must be increased in order to secure an acceptable capacitance. This problem is illustrated by reviewing a conventional method of manufacturing a capacitor.
FIGS. 1A and 1B are cross-sectional views of a semiconductor device. Referring now to FIG. 1A, a first interlayer insulating film 12 is formed on a semiconductor substrate 11 in which various components of a semiconductor device are formed through conventional processes. A given region of the first interlayer insulating film 12 is then etched to expose a junction region of the semiconductor substrate 11, thereby forming a first contact hole 100. Next, the first contact hole 100 is filled with a conductive material to form a charge storage electrode plug 13. After a second interlayer insulating film 14 is formed on the entire structure, a portion of the second interlayer insulating film 14 is removed to expose a charge storage electrode plug 13 by an etching process, thereby forming a second contact hole 200.
Currently, in order to secure an adequate capacitance of the capacitor, the height of the charge storage electrode must be high. As a result, the second interlayer insulating film 14 must be thick and, consequently, the process of forming the second contact hole 200 and the speed of removing the polymer generated upon etching becomes slower due to thickness of the interlayer insulating film 14. Further, the width of the lower portion of the second contact hole 200 is narrower than that of the upper portion of the second contact hole 200 resulting in an inclination face 15 at a lower portion of the second contact hole 200.
Referring now to FIG. 1B, a conductive material is deposited on the entire structure including the second contact hole 200. Next, a planarization process such as chemical mechanical polishing process is performed to remove the conductive material on top of the second interlayer insulating film 14, thus forming a charge storage electrode 16 within the second contact hole 200.
The charge storage electrode 16 has a V-shape which results in a reduced capacitance as opposed to when the charge storage electrode 16 has a vertical shape. Further, the contact area between the charge storage electrode plug 13 and the charge storage electrode 16 is reduced, thereby increasing the contact resistance. Therefore, the electrical characteristic of the capacitor is degraded.
A method of forming a contact hole and a method of forming a capacitor in a semiconductor device capable of preventing a reduction in the capacitance of the capacitor are disclosed where an impurity is doped into an interlayer insulating film and a difference in the doping concentration at upper and lower portions of the interlayer insulating film is controlled so that the etching rate at the lower portion of the interlayer insulating film is faster than that at the upper portion thereby obtaining a contact hole having a vertical shape as opposed to the inclined shape discussed above which results in an increased capacitance of the capacitor.
In order to obtain the vertically-shaped contact hole, a method of manufacturing a capacitor in a semiconductor device is disclosed which comprises forming interlayer insulating films on a semiconductor substrate in which various components for forming the semiconductor device are formed by means of common processes and doping at least one of the interlayer insulating film so that the concentration of the impurity at a lower portion of the interlayer insulating film being doped is higher than that at an upper portion of the interlayer insulating film being doped; removing a given region of the doped interlayer insulating film by means of an etching process; performing a wet cleaning process; forming a conductive material on the entire structure; performing a planarization process to form a plurality of independent charge storage electrodes; and forming a dielectric film and an upper electrode on the entire structure.
The impurity is preferably phosphorous or boron. The insulating films are preferably BPSG or PSG.
The supplying of the impurity while the insulating film is formed can include supplying an amount of impurity for a second interlayer insulating film that is smaller than that supplied when the first lower insulating film is formed to form a second insulating film with an impurity concentration which is lower than that of the first insulating film, and reducing the amount of the impurity supplied when a subsequent insulating film is formed to form an insulating film with an impurity concentration that is lower than that of underlying insulating films, in order to form the interlayer insulating films of a desired thickness.
By doping lower portions of the insulating film with a higher concentration of dopant and by doping upper portions of the insulating film with lower concentrations of dopant, the lower portions of the film are less dense than the upper portions and, consequently, etch at a faster rate resulting in a more vertical etching profile and a capacitor with improved properties.
The wet cleaning process may be performed using BOE or HF solution being oxide-etching solution.